ISBN-10:
0201500221
ISBN-13:
9780201500226
Pub. Date:
06/06/1997
Publisher:
Addison-Wesley
Application-Specific Integrated Circuits / Edition 1

Application-Specific Integrated Circuits / Edition 1

by Michael John Sebastian Smith
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Overview

This comprehensive book on application specific integrated circuits (ASICs) describes the latest methods in VLSI systems design. ASIC design, using commercial tools and predesigned cell libraries, is the fastest, most cost-effective, and least error prone method of IC design. As a consequence, ASICs and ASIC design methods have been increasingly popular in industry for a wide range of applications. The book covers semicustom and programmable ASIC types. After describing the fundamentals of digital logic design and the physical features of each ASIC type, the book turns to ASIC logic design -- design entry, logic synthesis, simulation, and test -- and then to physical design -- partitioning, floorplanning, placement, and routing. You will find in practical, well-explained detail, everything you need to know to understand the design of an ASIC, and everything you must do to begin and complete your own design.

Features:

  • Broad coverage that includes cell-based ICs, gate arrays, field-programmable gate arrays (FPGAs), and complex programmable logic devices (PLDs).
  • Examples, throughout the book, that have been checked with a wide range of commercial tools to ensure their accuracy and utility.
  • Separate chapters and appendixes on both Verilog and VHDL, including material from IEEE standards, that serve as a complete reference for high-level, ASIC-design entry.

As in other landmark VLSI books published by Addison-Wesley, the author's teaching expertise and industry experience illuminate the presentation of useful design methods. Any engineer, manager, or student who is working with ASICS in a design project, or who is simply interested in knowing more about the different ASIC types and design styles, will find this book to be an invaluable source, reference, and guide.

Product Details

ISBN-13: 9780201500226
Publisher: Addison-Wesley
Publication date: 06/06/1997
Series: VLSI Systems Series
Edition description: New Edition
Pages: 1040
Product dimensions: 7.80(w) x 9.64(h) x 1.67(d)

About the Author


Michael John Sebastian Smith is an ASIC researcher, designer, and educator. He teaches at the University of Hawaii and is a consultant at Compass Design Automation. Previously, he worked at the IBM T. J. Watson Research Center. Smith received B.A. and M.A. degrees from Queens' College, Cambridge University, and M.S. and Ph.D. degrees from Stanford University. In 1989, he was named a U.S. National Science Foundation Presidential Young Investigator.

Read an Excerpt


9.1.5 Nets

The schematics shown in Figure 9.4 contain both local nets and external nets. An example of a local net in Figure 9.4(b) is n1, the connection between the output terminal of the AND cell and to the OR cell orl. When the four copies of this circuit are placed in the parent cell FourBit in Figure 9.5(d), four copies of net n1 are created. Since the four nets named n1 are not actually electrically connected, even though they have the same name at the lowest hierarchical level, we must somehow find a way to uniquely identify each net.

The usual convention for naming nets in a hierarchical schematic uses the parent cell instance name as a prefix to the local net name . A special character (I : I '/' $, I '#' for example) that is not allowed to appear in names is used as a limiter to separate the net name from the cell instance name. Supposing that we drew the subschernatic for cell FourBit as shown in Figure 9.5(b), the four different nets labeled n1 might then become:

FourBit.L1:n1    FourBit.L2:n1   FourBit.L3:n1   FourBit.L4:n1

This naming is usually done automatically by the schematic-entry tool.

The schematic DLAT also contains three external nets: D, EN, and Q. The terminals on the symbol DLAT connect these nets to other nets in the hierarchical level above. For example, the signal Trigger: f lag in Figure 9.4(c) is also Trigger. DLAT:Q. Each schematic tool handles this situation differently, and life becomes especially difficult when we need to refer to these nodes from a simulator outside the schematic tool, for example. HDLs such as VHDL and Verilog have a very precise and well-defined standard for naming nets in hierarchical structures.

9.1.6 Schematic Entry for ASICs and PCBs

A symbol on a schematic may represent a component, which may contain component parts. You are more likely to come across the use of component-, in a PCB schematic. A component is slightly different from an ASIC library cell. A simple example of a component would be a TTL gate, an SN74LS00N that contains four 2-input NAND gates. We call an SN74LS00N a component and each of the individual NAND gates inside is a component part. Another common example of a component would be a resistor pack-a single package that contains several identical resistors.

In PCB design language a component label or name is a reference designator. A reference designator is a unique name attribute, such as R99, attached to each component. A reference designator, such as R99, has two pieces: an alpha prefix R and a numerical suffix 99. To understand the difference between reference designators and instance names, we need to look at the special requirements of PCB design.

PCBs usually contain packaged ASICs and other ICs that have pins that are soldered to a board. For rectangular, dual-in-line (DIP) packages the pins are numbered counterclockwise from the upper-left corner looking down on the package.

IC symbols have a pin number for each part in the package. For example, the TL 74174 hex D flip-flop with clear, contains six parts: six identical D flip-flops. The IC symbol representing this device has six PinNumber attribute entries for the D input corresponding to the six possible input pins. They are pins input corresponding to the six possible input pins. They are pins 3, 4, 6, 11, 13, and 14. 3, 4, 6, 11, 13, and 14.

When we need a flip-flop in our design, we use a symbol for a 74174 from a schematic library, suppose the symbol name is df f Clr We shall assign a unique instance name to the symbol, CarryFF Now suppose we need another, identical, flip-flop and we call this BitFF. We do not mind which of the six flip-flop parts in a 74174 we use for CarryFF and BitFF. In fact they do not even have to be in the same package. We shall delay the choice of assigning CarryFF and BitFF to specific packages until we get to the PCB routing step. So at this point on our schematic We do not even know the pin numbers for CarryFF and BitFF. For example the D input to CarryFF could be pin 3, 4, 6, 11, 13, or 14.

The number of wire crossings on a PCB is minimized by careful assignment of nts to packages and choice of parts within a package. So the placement- software may decide which part of which package to use for CarryFF and BitFF depending on which is easier to route. Then, only after the placement and routing is complete, are unique reference designators assigned to the component parts. Only at this point do we know where carryFF is actually located on the PCB referring to the reference designator, which points to a specific part in a specific package. Thus carryFF might be located in IC4 on our PCB. At this point we also know which pins are used for each symbol. So we now know, for example, that the D-input to CarryFF is pin 3 of IC4.

There is no process in ASIC design directly equivalent to the process of part assignment described above and thus no need to use reference designators. The reference-designator naming convention quickly becomes unwieldy if there are a large number of components in a design. For example, how will we find a NAND gate named X3146 in an ASIC schematic with 100 pages? Instead, for ASICs, we use a naming scheme based on hierarchy.

In large hierarchical ASIC designs it is difficult to provide a unique reference designator to each element. For this reason ASIC designs use instance names to identify the individual components. Meaningful names can be assigned to low-level components and also the symbols that represent hierarchy. We derive the component names by joining all of the higher level cell names together. A special character is used as a delimiter and separates each level. separates each level.

Examples of hierarchical instance names are:

cpu.alu.adder.and01
MotherBoard Cache: RAM4: ReadBit4: Inverter2

Table of Contents

1 INTRODUCTION TO ASICS

    1.1 Types of ASIC
      Full-Custom ASICs
      Standard-Cell? Based ASICs
      Gate-Array? Based ASICs
      Channeled Gate-Array
      Channelless Gate-Array
      Structured Gate-Array
      Programmable Logic Devices
      Field-Programmable Gate Arrays
    1.2 Design Flow
    1.3 Case Study
    1.4 Economics of ASICs
      Comparison Between ASIC Technologies
      Product Cost
      ASIC Fixed Costs
      ASIC Variable Costs
    1.5 ASIC Cell Libraries
    1.6 Summary
    1.7 Problems
    1.8 Bibliography
    1.9 References


2 CMOS LOGIC

    2.1 CMOS Transistors
      P-Channel Transistors
      Velocity Saturation
      SPICE Models
      Logic Levels
    2.2 The CMOS Process
      Sheet Resistance
    2.3 CMOS Design Rules
    2.4 Combinational Logic Cells
      Pushing Bubbles
      Drive Strength
      Transmission Gates
      Exclusive-OR Cell
    2.5 Sequential Logic Cells
      Latch
      Flip-Flop
      Clocked Inverter
    2.6 Datapath Logic Cells
      Datapath Elements
      Adders
      A Simple Example
      Multipliers
      Other Arithmetic Systems
      Other Datapath Operators
    2.7 I/O Cells
    2.8 Cell Compilers
    2.9 Summary
    2.10 Problems
    2.11 Bibliography
    2.12 References


3 ASIC LIBRARY DESIGN

    3.1 Transistors as Resistors
    3.2 Transistor Parasitic Capacitance
      Junction Capacitance
      Overlap Capacitance
      Gate Capacitance
      Input Slew Rate
    3.3 Logical Effort
      Predicting Delay
      Logical Area and Logical Efficiency
      Logical Paths
      Multistage Cells
      Optimum Delay
      Optimum Number of Stages
    3.4 Library-Cell Design
    3.5 Library Architecture
    3.6 Gate-Array Design
    3.7 Standard-Cell Design
    3.8 Datapath-Cell Design
    3.9 Summary
    3.10 Bibliography
    3.11 Problems
    3.12 References


4 PROGRAMMABLE ASICs

    4.1 The Antifuse
      Metal?Metal Antifuse
    4.2 Static RAM
    4.3 EPROM and EEPROM Technology
    4.4 Practical Issues
      FPGAs in Use
    4.5 Specifications
    4.6 PREP Benchmarks
    4.7 FPGA Economics
      FPGA Pricing
      Pricing Examples
    4.8 Summary
    4.9 Problems
    4.10 Bibliography
    4.11 References


5 PROGRAMMABLE ASIC LOGIC CELLS

    5.1 Actel
      ACT 1 Logic Module
      Shannon‚s Expansion Theorem
      Multiplexer Logic as Function Generators
      ACT 2 and ACT 3 Logic Modules
      Timing Model and Critical Path
      Speed Grading
      Worst-Case Timing
      Actel Logic Module Analysis
    5.2 Xilinx LCA
      XC3000 CLB
      XC4000 Logic Block
      XC5200 Logic Block
      Xilinx CLB Analysis
    5.3 Altera FLEX
    5.4 Altera MAX
      Logic Expanders
      Timing Model
      Power Dissipation in Complex PLDs
    5.5 Summary
    5.6 Problems
    5.7 Bibliography
    5.8 References


6 PROGRAMMABLE ASIC I/O CELLS

    6.1 DC Output
      Totem-Pole Output
      Clamp Diodes
    6.2 AC Output
      Supply Bounce
      Transmission Lines
    6.3 DC Input
      Noise Margins
      Mixed-Voltage Systems
    6.4 AC Input
      Metastability
    6.5 Clock Input
      Registered Inputs
    6.6 Power Input
      Power Dissipation
      Power-On Reset
    6.7 Xilinx I/O Block
      Boundary Scan
    6.8 Other I/O Cells
    6.9 Summary
    6.10 Problems
    6.11 Bibliography
    6.12 References


7 PROGRAMMABLE ASIC INTERCONNECT

    7.1 Actel ACT
      Routing Resources
      Elmore's Constant
      RC Delay in Antifuse Connections
      Antifuse Parasitic Capacitance
      ACT 2 and ACT 3 Interconnect
    7.2 Xilinx LCA
    7.3 Xilinx EPLD
    7.4 Altera MAX 5k and 7k
    7.5 Altera MAX 9k
    7.6 Altera FLEX
    7.7 Summary
    7.8 Problems
    7.9 Bibliography
    7.10 References


8 PROGRAMMABLE ASIC DESIGN SOFTWARE

    8.1 Design Systems
      Xilinx
      Actel
      Altera
    8.2 Logic Synthesis
      FPGA Synthesis
    8.3 The Halfgate ASIC
      Xilinx
      Actel
      Altera
      Comparison
    8.4 Summary
    8.5 Problems
    8.6 Bibliography
      FPGA Vendors
      Third-party Software
    8.7 References


9 LOW-LEVEL DESIGN ENTRY

    9.1 Schematic Entry
      Hierarchical Design
      The Cell Library
      Names
      Schematic Icons and Symbols
      Nets
      Schematic Entry for ASICs and PCBs
      Connections
      Vectored Instances and Buses
      Edit-in-Place
      Attributes
      Netlist Screener
      Schematic-Entry Tools
      Back-Annotation
    9.2 Low-level Design Languages
      ABEL
      CUPL
      PALASM
    9.3 PLA Tools
    9.4 EDIF
      EDIF Syntax
      An EDIF Netlist Example
      An EDIF Schematic Icon
      An EDIF Example
    9.5 CFI Design Representation
      CFI Connectivity Model
    9.6 Summary
    9.7 Bibliography
    9.8 Problems
    9.9 References


10 VHDL

    10.1 A Counter
    10.2 A 4-bit Multiplier
      An 8-bit Adder
      A Register-Accumulator
      Zero-Detector
      A Shift-Register
      A State Machine
      A Multiplier
      Packages and Test Bench
    10.3 Syntax and Semantics of VHDL
    10.4 Identifiers and Literals
    10.5 Entity and Architecture
    10.6 Packages and Libraries
      Standard Package
      Std_logic_1164 Package
      Textio Package
      Other Packages
      Creating Packages
    10.7 Interface Declaration
      Port Declaration
      Generics
    10.8 Type Declaration
    10.9 Other Declarations
      Object Declarations
      Subprogram Declarations
      Alias and Attribute Declarations
      Predefined Attributes
    10.10 Sequential Statements
      Wait Statement
      Assertion and Report Statements
      Assignment Statements
      Procedure Call
      If Statement
      Case Statement
      Other Sequential Control Statements
    10.11 Operators
    10.12 Arithmetic
      IEEE Synthesis Packages
    10.13 Concurrent Statements
      Block Statement
      Process Statement
      Concurrent Procedure Call
      Concurrent Signal Assignment
      Concurrent Assertion Statement
      Component Instantiation
      Generate Statement
    10.14 Execution
    10.15 Configurations and Specifications
    10.16 An Engine Controller
    10.17 Summary
    10.18 Bibliography
    10.19 Problems
    10.20 References


11 VERILOG HDL

    11.1 A Counter
    11.2 Basics of the Verilog Language
      Verilog Logic Values
      Verilog Data Types
      Other Wire Types
      Numbers
      Negative Numbers
      Strings
    11.3 Operators
      Arithmetic
    11.4 Hierarchy
    11.5 Procedures and Assignments
      Continuous Assignment Statement
      Sequential Block
      Procedural Assignments
    11.6 Timing Controls and Delay
      Timing Control
      Data Slip
      Wait Statement
      Blocking and Non-blocking Assignments
      Procedural Continuous Assignment
    11.7 Tasks and Functions
    11.8 Control Statements
      Case and If Statement
      Loop Statement
      Disable
      Fork and Join
    11.9 Logic Gate Modeling
      Built-in Logic Models
      User-defined Primitives
    11.10 Modeling Delay
      Net and Gate Delay
      Pin-to-pin Delay
    11.11 Altering Parameters
    11.12 A Viterbi Decoder
      Viterbi Encoder
      The Received Signal
      Testing the System
      Verilog Decoder Model
    11.13 Other Verilog Features
      Display Tasks
      File I/O Tasks
      Timescale, Simulation, and Timing Check Tasks
      PLA Tasks
      Stochastic Analysis Tasks
      Simulation Time Functions
      Conversion Functions
      Probability Distribution Functions
      Programming Language Interface
    11.14 Summary
    11.15 Bibliography
    11.16 Problems
      The Viterbi Decoder
    11.17 References
    


12 LOGIC SYNTHESIS

    12.1 A Logic-Synthesis Example
    12.2 A Comparator/MUX
      An Actel Version of the Comparator/MUX
    12.3 Inside a Logic Synthesizer
    12.4 Synthesis of the Viterbi Decoder
      ASIC I/O
      Flip-Flops
      The Top-Level Model
    12.5 Verilog and Logic Synthesis
      Verilog Modeling
      Delays in Verilog
      Blocking and Nonblocking Assignments
      Combinational Logic in Verilog
      Multiplexers In Verilog
      The Verilog Case Statement
      Decoders In Verilog
      Priority Encoder in Verilog
      Arithmetic in Verilog
      Sequential Logic in Verilog
      Component Instantiation in Verilog
      Datapath Synthesis in Verilog
    12.6 VHDL and Logic Synthesis
      Initialization and Reset
      Combinational Logic Synthesis in VHDL
      Multiplexers in VHDL
      Decoders in VHDL
      Adders in VHDL
      Sequential Logic in VHDL
      Instantiation in VHDL
      Shift Registers and Clocking in VHDL
      Adders and Arithmetic Functions
      Adder-subtracter and Don‚t Cares
    12.7 Finite-State Machine Synthesis
      FSM Synthesis in Verilog
      FSM Synthesis in VHDL
    12.8 Memory Synthesis
      Memory Synthesis in Verilog
      Memory Synthesis in VHDL
    12.9 The Multiplier
      Messages During Synthesis
    12.10 The Engine Controller
    12.11 Performance-Driven Synthesis
    12.12 Optimization of the Viterbi Decoder
    12.13 Summary
    12.14 Problems
    12.15 Bibliography
    12.16 References


13 SIMULATION

    13.1 The Different Types of Simulation
    13.2 The Comparator/MUX Example
      Structural Simulation
      Static Timing Analysis
      Gate-Level Simulation
      Net Capacitance
    13.3 Logic Systems
      Signal Resolution
      Logic Strength
    13.4 How Logic Simulation Works
      VHDL Simulation Cycle
      Delay
    13.5 Cell Models
      Primitive Models
      Synopsys Models
      Verilog Models
      VHDL Models
      VITAL Models
      SDF in Simulation
    13.6 Delay Models
      Using a Library Data Book
      Input-Slope Delay Model
      Limitations of Logic Simulation
    13.7 Static Timing Analysis
      Hold Time
      Entry Delay
      Exit Delay
      External Setup Time
    13.8 Formal Verification
      An Example
      Understanding Formal Verification
      Adding an Assertion
      Completing a Proof
    13.9 Switch-Level Simulation
    13.10 Transistor-Level Simulation
      A PSpice Example
      SPICE Models
    13.11 Summary
    13.12 Problems
    13.13 Bibliography
    13.14 References


14 TEST

    14.1 The Importance of Test
    14.2 Boundary-Scan Test
      BST Cells
      BST Registers
      Instruction Decoder
      TAP Controller
      Boundary-Scan Controller
      A Simple Boundary-Scan Example
      BSDL
    14.3 Faults
      Reliability
      Fault Models
      Physical Faults
      Stuck-at Fault Model
      Logical Faults
      IDDQ Test
      Fault Collapsing
      Fault Collapsing Example
    14.4 Fault Simulation
      Serial Fault Simulation
      Parallel Fault Simulation
      Concurrent Fault Simulation
      Nondeterministic Fault Simulation
      Fault-Simulation Results
      Fault-Simulator Logic Systems
      Hardware Acceleration
      A Fault Simulation Example
      Fault Simulation in an ASIC Design Flow
    14.5 Automatic Test-Pattern Generation
      The D-Calculus
      A Basic ATPG Algorithm
      The PODEM Algorithm
      Controllability and Observability
    14.6 Scan Test
    14.7 Built-in Self-test
      LFSR
      Signature Analysis
      A Simple BIST Example
      Aliasing
      LFSR Theory
      LFSR Example
      MISR
    14.8 A Simple Test Example
      Test Logic Insertion
      How the Test Software Works
      ATVG and Fault Simulation
      Test Vectors
      Production Tester Vector Formats
      Test Flow
    14.9 The Viterbi Decoder Example
    14.10 Summary
    14.11 Problems
    14.12 Bibliography
    14.13 References


15 ASIC CONSTRUCTION

    15.1 Physical Design
    15.2 CAD Tools
      Methods and Algorithms
    15.3 System Partitioning
    15.4 Estimating ASIC Size
    15.5 Power Dissipation
      Switching Current
      Short-Circuit Current
      Subthreshold and Leakage Current
    15.6 FPGA Partitioning
      ATM Simulator
      Automatic Partitioning with FPGAs
    15.7 Partitioning Methods
      Measuring Connectivity
      A Simple Partitioning Example
      Constructive Partitioning
      Iterative Partitioning Improvement
      The Kernighan?Lin Algorithm
      The Ratio-Cut Algorithm
      The Look-ahead Algorithm
      Simulated Annealing
      Other Partitioning Objectives
    15.8 Summary
    15.9 Problems
    15.10 Bibliography
    15.11 References


16 FLOORPLANNING AND PLACEMENT

    16.1 Floorplanning
      Floorplanning Goals and Objectives
      Measurement of Delay in Floorplanning
      Floorplanning Tools
      Channel Definition
      I/O and Power Planning
      Clock Planning
    16.2 Placement
      Placement Terms and Definitions
      Placement Goals And Objectives
      Measurement of Placement Goals and Objectives
      Placement Algorithms
      Eigenvalue Placement Example
      Iterative Placement Improvement
      Placement Using Simulated Annealing
      Timing-Driven Placement Methods
      A Simple Placement Example
    16.3 Physical Design Flow
    16.4 Information Formats
      SDF for Floorplanning and Placement
      PDEF
      LEF and DEF
    16.5 Summary
    16.6 Problems
    16.7 Bibliography
    16.8 References


17 ROUTING

    17.1 Global Routing
      Goals and Objectives
      Measurement of Interconnect Delay
      Global Routing Methods
      Global Routing Between Blocks
      Global Routing Inside Flexible Blocks
      Timing-Driven Methods
      Back-annotation
    17.2 Detailed Routing
      Goals and Objectives
      Measurement of Channel Density
      Algorithms
      Left-Edge Algorithm
      Constraints and Routing Graphs
      Area-Routing Algorithms
      Multilevel Routing
      Timing-Driven Detailed Routing
      Final Routing Steps
    17.3 Special Routing
      Clock Routing
      Power Routing
    17.4 Circuit Extraction and DRC
      SPF, RSPF and DSPF
      Design Checks
      Mask Preparation
    17.5 Summary
    17.6 Problems
    17.7 Bibliography
    17.8 References


APPENDIX A VHDL RESOURCES
    A.1 BNF
    A.2 VHDL Syntax
    A.3 BNF Index
    A.4 Bibliography
    A.5 References


APPENDIX B VERILOG HDLRESOURCES
    B.1 Explanation of the Verilog HDL BNF
    B.2 Verilog HDL Syntax
    B.3 BNF Index
    B.4 Verilog HDL LRM
    B.5 Bibliography
    B.6 References


GLOSSARY OF SYMBOLS AND ACRONYMS


INDEX

Preface

In 1988 I began to teach full-custom VLSI design. In 1990 I started teaching ASIC design instead, because my students found it easier to get jobs in this field. I wrote a proposal to The National Science Foundation (NSF) to use electronic distribution of teaching material. Dick Lyon helped me with preparing the first few CD-ROMs at Apple, but Chuck Seitz, Lynn Conway, and others explained to me that I was facing a problem that Carver Mead and Lynn had experienced in trying to get the concept of multichip wafers adopted. It was not until the publication of the Mead-Conway text that people accepted this new idea. It was suggested that I must generate interest using a conventional format before people would use my material in a new one (CD-ROM or the Internet). In 1992 I stopped writing papers and began writing this book-a result of my experiments in computer-based education. I have nearly finished this book twice. The first time was a copy of my notes. The second time was just before the second edition of Weste and Eshragian was published-a hard act to follow. In order to finish in 1997 I had to stop updating and including new ideas and material and now this book consists of three parts: Chapters 1-8 are an introduction to ASICs, 9-14 cover ASIC logical design, and 15-17 cover the physical design of ASICs.

The book is intended for a wide audience. It may be used in an undergraduate or graduate course. It is also intended for those in industry who are involved with ASICs. Another function of this book is an "ASIC Encyclopedia," and therefore I have kept the background material needed to a minimum. The book makes extensiveuse of industrial tools and examples. The examples in Chapters 2 and 3 use tools and libraries from MicroSim (PSpice), Meta Software (HSPICE), Compass Design Automation (standard-cell and gate-array libraries), and Tanner Research (L-Edit). The programmable ASIC design examples in Chapter 4-8 use tools from Compass, Synopsys, Actel, Altera, and Xilinx. The examples in Chapter 9 (covering low-level design entry) used tools from Exemplar, MINC, AMD, UC Berkeley, Compass, Capilano, Mentor Graphics Corporation, and Cadence Design Automation. The VHDL examples in Chapter 10 were checked using QuickVHDL from Mentor, V-System Plus from Model Technology, and Scout from Compass. The Verilog examples in Chapter 11 were checked using Verilog-XL from Cadence, V-System Plus, and VeriWell from Wellspring Solutions. The logic synthesis examples in Chapter 12 were checked with the ASIC Synthesizer product family from Compass and tools from Mentor, Synopsys, and UC Berkeley. The simulation examples in Chapter 13 were checked with QuickVHDL, V-System/Plus, PSpice, Verilog-XL, DesignWorks from Capilano Computing, CompassSim, QSim, MixSim, and HSPICE. The test examples in Chapter 14 were checked using test software from Compass, Cadence, Mentor, Synopsys and Capilano's DesignWorks. The physical design examples in Chapters 15-17 were generated and tested using Preview, Gate Ensemble, and Cell Ensemble (Cadence) as well as ChipPlanner, ChipCompiler, and PathFinder (Compass). All these tools are installed at the University of Hawaii.

I wrote the text using FrameMaker. This allows me to project the text and figures using an LCD screen and an overhead projector. I used a succession of Apple Macintosh computers: a PowerBook 145, a 520, and lastly a 3400 with 144 MB of RAM, which made it possible for me to create updates to the index in just under one minute. Equations are "live" in FrameMaker. Thus, can be updated in a lecture and the new result displayed. The circuit layouts are color EPS files with enhanced B&W PICT previews created using L-Edit from Tanner Research. All of the Verilog and VHDL code examples, compiler and simulation input/output, and the layout CIF that were used in the final version are included as conditional (hidden) text in the FrameMaker document, which is approximately 200 MB and just over 6,000 pages (my original source material spans fourteen 560 MB optical disks). Software can operate on the hidden text, allowing, for example, a choice of simulators to run the HDL code live in class. I converted draft versions of the VHDL and Verilog LRMs and related standards to FrameMaker and built hypertext links to my text, but copyright problems will have to be solved before this type of material may be published. I drew all the figures using FreeHand. They are "layered" allowing complex drawings to be built-up slowly or animated by turning layers on or off. This is difficult to utilize in book form, but can be done live in the classroom.

A course based on FPGAs can use Chapter 1 and Chapters 4-8. A course using commercial semicustom ASIC design tools may use Chapters 1-2 or Chapters 1-3 and then skip to Chapter 9 if you use schematic entry, Chapter 10 (if you use VHDL), or Chapter 11 (if you use Verilog) together with Chapter 12. All classes can use Chapters 13 and 14. FPGA-based classes may skim Chapters 15-17, but classes in semicustom design should cover these chapters. The chapter dependencies-Y (X) means Chapter Y depends on X-are approximately: 1, 2(1), 3(2), 4(2), 5(4), 6(5), 7(6), 8(7), 9(2), 10(2), 11(2), 12(10 or 11), 13(2), 14(13), 15(2), 16(15), 17(16).

I used the following references to help me with the orthography of complex terms, style, and punctuation while writing: Merriam-Webster's Collegiate Dictionary, 10th edition, 1996, Springfield, MA: Merriam-Webster, ISBN 0-87779-709-9, PE1628.M36; The Chicago Manual of Style, 14th edition, Chicago: University of Chicago Press, 1993, ISBN 0-226-10389-7, Z253.U69; and Merriam-Webster's Standard American Style Manual, 1985, Springfield, MA: Merriam-Webster, ISBN 0-87779-133-3, PN147.W36. A particularly helpful book on technical writing is BUGS in Writing by Lyn DuprE, 1995, Reading, MA: Addison-Wesley, ISBN 0-201-60019-6, PE1408.D85 (this book grew from Lyn DuprE's unpublished work, Style SomeX, which I used).

The bibliography at the end of each chapter provides alternative sources if you cannot find what you are looking for. I have included the International Standard Book Number (ISBN) and Library of Congress (LOC) Call Number for books, and the International Standard Serial Number (ISSN) for journals (see the LOC information system, LOCIS, at http://www.loc.gov). I did not include references to material that I could not find myself (except where I have noted in the case of new or as yet unpublished books). The electronic references given in this text have (a last) access date of 4/19/97 and omit enclosing <> if the reference does not include spaces.

I receive a tremendous level of support and cooperation from industry in my work. I thank the following for help with this project: Cynthia Benn and Lyn DuprE for editing; Helen Goldstein, Peter Gordon, Susan London-Payne, Tracy Russ, and Juliet Silveri, all at Addison-Wesley; Matt Bowditch and Kim Arney at Argosy; Richard Lyon, Don North, William Rivard, Glen Stone, the managers of the Newton group, and many others at Apple Computer who provided financial support; Apple for providing support in the form of software and computers; Bill Becker, Fern Forcier, Donna Isidro, Mike Kliment, Paul McLellan, Tom Schaefer, Al Stein, Rich Talburt, Bill Walker, and others at Compass Design Automation and VLSI Technology for providing the opportunity for me to work on this book over many years and allowing me to test material inside these companies and on lecture tours they sponsored; Chuck Seitz at Caltech; Joseph Cavallaro, Bernie Chern, Jerry Dillion, Mike Foster, and Paul Hulina at the NSF; the NSF for financial support with a Presidential Young Investigator Award; Jim Rowson and Doug Fairbairn; Constantine Anagnostopolous, Pin Tschang and members of the ASIC design groups at Kodak for financial support; the disk-drive design group at Digital Equipment Corp. (Massachusetts), Hewlett-Packard, and Sun Microsystems for financial support; Ms. MOSIS and all of the staff at MOSIS who each have helped me at one point or another by providing silicon, technical support, and documentation; Bob Brodersen, Roger Howe, Randy Katz, and Ed Lee of UC Berkeley for help while I was visiting UCB; James Plummer of Stanford, for providing me with access to the Terman Engineering Library as a visiting scholar, as well as Abbas El Gamal and Paul Losleben, also at Stanford, for help on several occasions; Don Bouldin at University of Tennessee; Krzysztof Kozminski at MCNC for providing Uncle layout software; Gershom Kedem at Duke University for the public domain tools his group has written; Sue Drouin, JosE De Castro, and others at Mentor Graphics Corporation in Oregon for providing documentation and tools; Vahan Kasardjhan, Gail Grego, Michele Warthen, Steve Gardner, and others at the University Program at Cadence Design Automation in San Jose who helped with tools, documentation, and support; Karen Dorrington and the Cadence group in Massachusetts; Andy Haines, Tom Koppin, Sherri Mieth, Velma Miller, Robert Nalesnik, Mike Sarpa, Telle Whitney, and others at Actel for software, hardware, parts, and documentation; Peter Alfke, Leslie Baxter, Brad Fawcett, Chris Kingsley, Karlton Lau, Rick Mitchell, Scott Nance, and Richard Ravel at Xilinx for support, parts, software, and documentation; Greg Hedmann at NorComp for data on FPGAs; Anna Acevedo, Suzanne Bailey, Antje MacNaughton, Richard Terrell, and Altera for providing software, hardware programmers, parts, and documentation; the documentation group and executive management at LSI Logic for tools, libraries, and documentation; Toshiba, NEC, AT&T/NCR, Lucent, and Hitachi (for documentation); NEC for their visiting scholar program at UH; Fred Furtek, Oscar Naval, and Claire Pinkham at Concurrent Logic, Randy Fish at Crosspoint, and Gary Banta at Plus Logic-all for documentation; Paul Titchener and others at Comdisco (now part of Cadence Design Automation) for providing design tools; John Tanner and his staff at Tanner Research for providing their tools and documentation; Mahendra Jain and Nanci Magoun, who let me debug early prototypes at the IDEA conference organized by ASIC Technology and News; Exemplar for providing documentation on its tools; MINC for providing a copy of its FPGA software and documentation; Claudia Traver and Synopsys for tools and documentation; Mentor Graphics Corporation for providing its complete range of software; Alain Hanover and others at ViewLogic for providing tools; Mary Shepherd and Jerry Walker at IEEE for help with permissions; Meta Software for providing HSPICE; Chris Dewhurst and colleagues at Capilano Computing for its design tools; Greg Seltzer (Model Technology) and Charley Rowley for providing V-System Plus with online documentation prototypes; Farallon and Telebit for the software and hardware I used for early experiments with telelectures. Many research students at the University of Hawaii helped me throughout this project including: Chin Huang, Clem Portmann, Christeen Gray, Karlton Lau, Jon Otaguro, Moe Lwin, Troy Stockstad, Ron Jorgenson, Derwin Mattos, William Rivard, Wendy Ching, Anil Aggrawal, Sudhakar Jilla, Linda Xu, Angshuman Saha, Harish Pareek, Claude van Ham, Wen Huang, Kumar Vadhri, Yan Zhong, Yatin Acharya, and Barana Ranaweera. Each of the classes that used early versions of this text at the University of Hawaii at Manoa have also contributed by finding errors. The remaining errors are mine.

Michael John Sebastian Smith
Palo Alto and Honolulu, 1997

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